The present invention generally relates to methods and devices for refreshing dynamic semiconductor memory devices having an error checking and correcting circuit (hereinafter simply referred to as an ECC circuit), and more particularly to a method and device for selectively performing in the dynamic semiconductor memory device refresh operations with and without an error checking and correcting operation of the ECC circuit.
Recently, as the integration density of a metal oxide semiconductor (MOS) dynamic random access memory (DRAM) is improved from 64 Kb to 256 Kb and 1 Mb, the storage capacitance of one memory cell becomes small. As a result, the soft error rate caused by .alpha.-particles becomes large. A DRAM having a built-in (or on-chip) ECC circuit for the purpose of reducing such soft error rate is known. For example, such a DRAM is described in "A Submicron VLSI Memory with a 4b-at-a-time Built-in ECC Circuit" by J. Yamada, T. Mano, J. Inoue and S. Nakajima, ISSCC Technical Digest, pp 104-105, 1984, "A Self-correcting Circuit in 1Mb DRAM" by Date, Yamada and Mano, Institute of Electronics and Communication Engineers (Denshi Tsushin Gakkai), Material of the Society for the Study of Semiconductor Transistor, SSD84-21, pp 51-58, May 1984, and "A Submicron VLSI Memory with a 4b-at-a-time Built-in ECC Circuit" by J. Yamada, T. Mano, J. Inoue, S. Nakajima and T. Matsuda, IEEE Journal of Solid State Circuits, Vol. SC19, No. 5, pp 627-633, October 1984.
In the DRAM having the built-in ECC circuit, a plurality of memory cells at specific addresses of a memory cell array are divided into horizontal and vertical cell groups according to a predetermined method, and the so-called bi-directional parity checking (or horizontal-vertical parity checking) is employed wherein parity check information for each of the horizontal and vertical cell groups is stored in a cell array for the parity checking. When reading out the data from a certain memory cell, the parities of the memory cells belonging to the same horizontal and vertical cell groups as the certain memory cell are subjected to an arithmetic operation. Parities obtained as a result of the arithmetic operation are compared with corresponding parities stored in the cell array for the parity checking, and the data read out from the certain memory cell is corrected depending on the result of the comparison.
The error checking and correcting operation of the ECC circuit is performed simultaneously with a refresh operation in the DRAM. In other words, the so-called ECC patrol is performed by a read modify write mode in which the stored data in a specific memory cell is checked as the refresh operation is performed and the data is replaced by a correct data when an error is detected. The ECC patrol is an operation in which the error checking and correcting operation is performed for each unit of coded information. For example, in the case of a plurality of memory cells arranged in a matrix arrangement, rows (word lines) are successively designated by a refresh address counter in order to perform the refresh operation, and columns (bit line pairs) are successively designated by an ECC column address counter in order to perform the ECC patrol. In this case, when it is assumed that the refresh cycle is 8 msec and a bit length of one column is 1024 (that is, in the case of a 1 Mb DRAM), the period of the ECC patrol is approximately 8 sec. The count in the ECC column address counter is incremented for each refresh cycle, and thus, and the stored data in one column are checked and replaced by correct data in case of errors for each refresh cycle. As a result, one ECC patrol for all of the memory cells of the DRAM, that is, the period of the ECC patrol, can be obtained by (refresh cycle).times.(bit length of one column) and the period of the ECC patrol in the case of the 1 Mb DRAM having the bit length of 1024 in one column is approximately 8 sec as described above.
When the ECC patrol is performed in the refresh mode, the time it takes to perform the refresh operation (that is, the so-called refresh overhead time) becomes considerably long compared to the refresh overhead time of a DRAM not having the built-in ECC circuit. Hence, the DRAM having the built-in ECC circuit suffers a disadvantage in that the refresh overhead time is extremely long. In the case of the DRAM not having the built-in ECC circuit, the refresh operation comprises the steps of selecting the word lines by the refresh address counter and driving the memory cells and sense amplifiers, and thereafter applying an initial voltage which is the same as that at the time of a write operation. In other words, the refresh operation of the DRAM not having the built-in ECC circuit simply comprises a first half of a read operation. On the other hand, in the case of the DRAM having the built-in ECC circuit, the refresh operation comprises in addition to the above steps the steps of checking the stored data and driving the write circuit.
During the refresh operation, that is, during the refresh overhead time, it is impossible to make access to the memory cells so as to perform the normal read and write operations. Therefore, it is desirable to shorten the refresh overhead time in order to improve the utilization efficiency of the memory device. Furthermore, in the case of the DRAM having the built-in ECC circuit, column-side (or Y-side) circuits such as a clock generator, column decoders and the ECC circuit must be driven during the refresh operation, and there is a problem in that the power consumption is higher than that of the DRAM not having the built-in ECC circuit.